1. Field of the Invention
The present invention generally relates to semiconductor device and method for forming the same, and more specifically, to semiconductor device and method for forming the same wherein a space formed by removing a SiGe epitaxial layer below the gate electrode is filled up by a buried insulating layer and the gate electrode surrounds a Si epitaxial layer to increase the current driving capability of the device and to improve short channel effect.
2. Description of the Prior Art
FIG. 1 is a top-view illustrating a layout of a conventional semiconductor device and FIG. 2 is a cross-sectional diagram taken along the lines I-I′ and II-II′ of FIG. 1.
Referring to FIGS. 1 and 2, the conventional semiconductor device comprises a semiconductor substrate 10 having an active region defined by a device isolation film 25. A stacked structure of a buried insulating film 50 and a Si epitaxial layer 20 is disposed on the surface of the semiconductor substrate 10. A channel region (not shown) and LDD regions 40 adjacent to the channel region are formed in the Si epitaxial layer 20. A stacked structure of a gate oxide film pattern 30a, a gate electrode 35a and a hard mask insulating film pattern 37a is disposed on the channel region. A sidewall spacer 45 is disposed on a sidewall of the stacked structure. Source/drain regions (not shown) are disposed in the active region at both sides of the sidewall spacer 45.
FIGS. 3a through 3f are cross-sectional diagrams taken along the lines I-I′ and II-II′ of FIG. 1, illustrating a conventional method for manufacturing the semiconductor device of FIG. 1.
Referring to FIG. 3a, a SiGe epitaxial layer 15 and a Si epitaxial layer 20 are sequentially formed on a semiconductor substrate 10. Thereafter, a device isolation film 25 defining an active region is formed on the semiconductor substrate 10.
Referring to FIG. 3b, an impurity is implanted into the Si epitaxial layer 20 to form a channel region (not shown). A gate oxide film 30, a conductive layer 35 for gate electrode and a hard mask insulating film 37 are then sequentially formed on the entire surface of the semiconductor substrate 10. The gate oxide film 30, the conductive layer 35 and the hard mask insulating film 37 are patterned to form a stacked structure of a gate oxide film pattern 30a, a gate electrode 35a and a hard mask insulating film pattern 37a. 
Next, LDD regions 40 are formed in the Si epitaxial layer 20 at both sides of the gate electrode 35a. 
Referring to FIG. 3d, a sidewall spacer 45 is formed on a sidewall of the stacked structure. Thereafter, the Si epitaxial layer 20, the SiGe epitaxial layer 15 and a predetermined depth of the semiconductor substrate 10 at both side of the sidewall spacer 45 are etched away to expose LDD region 40, a sidewall of the SiGe epitaxial layer 15, and a sidewall and a surface of the semiconductor substrate 10.
Referring to FIG. 3e, the SiGe epitaxial layer 15 under the gate electrode 35a is wet etched to form a space under the Si epitaxial layer 20, i.e. under the LDD region 40 and the channel region.
Referring to FIG. 3f, an insulating film (not shown) is formed in the space, the exposed surfaces of the Si epitaxial layer 20 and the semiconductor substrate 100. The insulating film is then wet etched to form a buried insulating film 50 filling the space.
Referring to FIG. 3g, a silicon layer 55 is grown in the active region at both sides of the sidewall spacer where the Si epitaxial layer 20, the SiGe epitaxial layer 150 and a predetermined depth of the semiconductor substrate 10 have been removed. An impurity is then implanted to form source/drain regions in the silicon layer (not shown).
In accordance with the conventional semiconductor device and method for forming the same, the gate electrode is disposed only on the channel region formed in the Si epitaxial layer so that a short channel effect is increased. In order to decrease the short channel effect, the thickness of the channel region must be decreased. However, since the thickness of the channel region determines the characteristics of a MOSFET, the characteristics of a MOSFET largely vary as the thickness of the channel region is varied.